An AJC is described in our European patent application No. 97903456.8 based on International patent application, publication No. WO 97/305 16. The described AJC circuit provides a unique way of reducing phase noise or time jitter on a frequency source, typically 20 dB or more for the or each (fully cascaded) stage. FIGS. 1(a) to 1(c) of the accompanying drawings illustrate the principle of operation of this earlier AJC. FIG. 1(a) is a block circuit diagram of the system described in the earlier patent application, FIG. 1(b) shows an input pulse train with jitter (shown in broken outline) on the central pulse and FIG. 1(c) shows the corresponding integrator output (Op2) and the comparator switching level (Op3).
The present invention provides an improvement over this earlier AJC. Because the implementation of the core part of the improved AJC requires no d.c. power the term adiabatic anti-jitter circuit (AAJC) will be used hereinafter.
According to the invention there is provided an anti-jitter circuit for reducing time jitter in an input pulse train comprising:
an integrator charge storage means,
charging means for deriving from the input pulse train at least one charge packet during each cycle of the input pulse train and for supplying the charge packets to the integrator charge storage means, and
discharging means for continuously discharging the integrator charge storage means,
the charging means and the discharging means being operative to create on the integrator charge storage means a time varying voltage waveform having a mean d.c. voltage level, and
means for comparing said time varying voltage waveform with said mean d.c. voltage level and deriving an output pulse train as a result of the comparison.